Overview
========
This WDOG Example project demonstrates an eight second watchdog that times
out and triggers a reset.

NOTE: Please notice that because WDOG control registers are write-once only.
      And for the field WDT, once software performs a write "1" operation
	  to this bit, it can not be reset/cleared until the next POR, this
	  bit does not get reset/ cleared due to any system reset. So the
	  WDOG_Init function can be called only once after power reset when
	  WDT set, and the WDOG_Disable function can be called only once
	  after reset.

NOTE: It is very unlikely that this example can be executed in a debugger

NOTE: After flashing this example you have to put the board in ISP mode
      to be able to flash it again as the watchdog keeps resetting the
      connection to the debugger. See the User Manual on how to put the
      board in ISP mode.

Toolchain supported
===================
- IAR embedded Workbench  8.50.9
- Keil MDK  5.33
- GCC ARM Embedded  9.3.1
- MCUXpresso  11.3.0

Hardware requirements
=====================
- Mini/micro USB cable
- Embedded Artists iMX RT1062 Developer's Kit
- Personal Computer

Board settings
==============
No special settings are required.

Prepare the Demo
================
1.  Connect a USB cable between the host PC and the OpenSDA USB port on the target board. 
2.  Open a serial terminal with the following settings:
    - 115200 baud rate
    - 8 data bits
    - No parity
    - One stop bit
    - No flow control
3.  Download the program to the target board.
4.  Either press the reset button on your board or launch the debugger in your IDE to begin running the demo.

Running the demo
================
These instructions are displayed/shown on the terminal window:
~~~~~~~~~~~~~~~~~~~~~~~
******** System Start ********
System reset by: Power On Reset!

- Testing system reset by WDOG timeout.
--- wdog Init done, timeout=8s ---
Waiting for WDOG to reset...
Waiting for WDOG to reset...
Waiting for WDOG to reset...
Waiting for WDOG to reset...
Waiting for WDOG to reset...

******** System Start ********
System reset by: Power On Reset!

- Testing system reset by WDOG timeout.
--- wdog Init done, timeout=8s ---
Waiting for WDOG to reset...
Waiting for WDOG to reset...
...

~~~~~~~~~~~~~~~~~~~~~
Customization options
=====================

