/*
** ###################################################################
**     Processors:          MIMXRT1176AVM8A_cm7
**                          MIMXRT1176CVM8A_cm7
**                          MIMXRT1176DVMAA_cm7
**
**     Compiler:            IAR ANSI C/C++ Compiler for ARM
**     Reference manual:    IMXRT1170RM, Rev E, 12/2019
**     Version:             rev. 0.1, 2018-03-05
**     Build:               b200828
**
**     Abstract:
**         Linker file for the IAR ANSI C/C++ Compiler for ARM
**
**     Copyright 2016 Freescale Semiconductor, Inc.
**     Copyright 2016-2020 NXP
**     All rights reserved.
**
**     SPDX-License-Identifier: BSD-3-Clause
**
**     http:                 www.nxp.com
**     mail:                 support@nxp.com
**
** ###################################################################
*/

define symbol __ram_vector_table_size__        =  isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
define symbol __ram_vector_table_offset__      =  isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;

define symbol m_interrupts_start       = 0x30002000;
define symbol m_interrupts_end         = 0x300023FF;

define symbol m_text_start             = 0x30002400;
define symbol m_text_end               = 0x30FFFFFF;

define symbol m_interrupts_ram_start   = 0x20000000;
define symbol m_interrupts_ram_end     = 0x20000000 + __ram_vector_table_offset__;

define symbol m_data_start             = m_interrupts_ram_start + __ram_vector_table_size__;
define symbol m_data_end               = 0x2003FFFF;

define symbol m_ncache_start                   = 0x81000000;
define symbol m_ncache_end                     = 0x81FFFFFF;

define exported symbol __NCACHE_REGION_START   = m_ncache_start;
define exported symbol __NCACHE_REGION_SIZE    = m_ncache_end - m_ncache_start + 1;

define exported symbol m_boot_hdr_conf_start = 0x30000400;
define symbol m_boot_hdr_ivt_start           = 0x30001000;
define symbol m_boot_hdr_boot_data_start     = 0x30001020;
define symbol m_boot_hdr_dcd_data_start      = 0x30001030;

/* Sizes */
if (isdefinedsymbol(__stack_size__)) {
  define symbol __size_cstack__        = __stack_size__;
} else {
  define symbol __size_cstack__        = 0x0400;
}

if (isdefinedsymbol(__qul_preprocess_cache_size__)) {
    define symbol m_preprocess_cache_size = __qul_preprocess_cache_size__;
} else {
    define symbol m_preprocess_cache_size = 512K;
}

define exported symbol __VECTOR_TABLE          = m_interrupts_start;
define exported symbol __VECTOR_RAM            = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;

define memory mem with size = 4G;
define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
                          | mem:[from m_text_start to m_text_end];
define region SDRAM_region =  mem:[from 0x80000000 size 8M];
define region PRELOAD_region = mem:[from 0x80800000 size 8M];
define exported symbol __preloadRamStart = start(PRELOAD_region);
define exported symbol __preloadRamEnd = start(PRELOAD_region) + size(PRELOAD_region);
define region OCRAM2_region = mem:[from 0x202C0000 size 512K];
define region DATA_region =   mem:[from m_data_start to m_data_end];
define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
define block CSTACK     with alignment = 8, expanding size { };
define block HEAP       with alignment = 8, expanding size { };
define block NCACHE_HEAP with alignment = 8, expanding size { };
define block RW         { first readwrite, section m_usb_dma_init_data };
define block ZI         with alignment = 4  { first zi, section m_usb_dma_noninit_data };
define block NCACHE_VAR { section NonCacheable , section NonCacheable.init };
define block RO with alignment = 4 { readonly };
define block ResourceData with alignment = 8, fixed order { readonly section QulFontResourceData,
                                                            readonly section QulResourceData
                                                           };
define block ModuleResourceData with alignment = 8 { readonly section QulModuleResourceData_init };
define block QulPreprocessCache with alignment = 8, size = m_preprocess_cache_size { };

initialize by copy { readwrite, section .textrw };
initialize manually { section QulModuleResourceData };
do not initialize  { section .noinit };

"INTVEC":
place at address mem: m_interrupts_start    { readonly section .intvec };

"HDR_CONF":
place at address mem:m_boot_hdr_conf_start { section .boot_hdr.conf };
"HDR_IVT":
place at address mem:m_boot_hdr_ivt_start { section .boot_hdr.ivt };
"HDR_BOOT":
place at address mem:m_boot_hdr_boot_data_start { readonly section .boot_hdr.boot_data };
"HDR_DCD":
place at address mem:m_boot_hdr_dcd_data_start { readonly section .boot_hdr.dcd_data };

keep{ section .boot_hdr.conf, section .boot_hdr.ivt, section .boot_hdr.boot_data, section .boot_hdr.dcd_data };

"TEXT":
place in TEXT_region                        { block RO, block ModuleResourceData, block ResourceData };

"SDRAM_RW":
place in SDRAM_region                       { block RW };
"SDRAM_ZI":
place in SDRAM_region                       { block ZI };

"QulModuleResourceData":
place in SDRAM_region                       { section QulModuleResourceData };

"QulPreprocessCache":
place in SDRAM_region                       { block QulPreprocessCache };

"SDRAM_HEAP":
place in SDRAM_region                     { last block HEAP };

"STACK":
place in OCRAM2_region                      { last block CSTACK };

"NCACHE_VAR":
place in NCACHE_region                      { block NCACHE_VAR };

"NCACHE_HEAP":
place in NCACHE_region                      { last block NCACHE_HEAP };
