diff --git a/component/phy/SConscript b/component/phy/SConscript
index 1cec8d7..9c591b7 100644
--- a/component/phy/SConscript
+++ b/component/phy/SConscript
@@ -8,8 +8,10 @@ cwd = GetCurrentDir()
 CPPPATH = [cwd, cwd + "/mdio/enet"]
 
 if GetDepend(['SOC_IMXRT1170_SERIES']):
-    src += ['device/phyrtl8211f/fsl_phyrtl8211f.c']
-    CPPPATH += [cwd + "/device/phyrtl8211f"]
+#    src += ['device/phyrtl8211f/fsl_phyrtl8211f.c']
+#    CPPPATH += [cwd + "/device/phyrtl8211f"]
+    src += ['device/phyar8031ds/fsl_phyar8031ds.c']
+    CPPPATH += [cwd + "/device/phyar8031ds"]
 else:
     src += ['device/phyksz8081/fsl_phyksz8081.c']
     CPPPATH += [cwd + "/device/phyksz8081"]
diff --git a/component/phy/device/phyar8031ds/fsl_phyar8031ds.c b/component/phy/device/phyar8031ds/fsl_phyar8031ds.c
new file mode 100644
index 0000000..adbf56d
--- /dev/null
+++ b/component/phy/device/phyar8031ds/fsl_phyar8031ds.c
@@ -0,0 +1,471 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_phyar8031ds.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Defines the PHY AR8031DS vendor defined registers. */
+#define PHY_SPECIFIC_STATUS_REG 0x11U /*!< The PHY specific status register. */
+#define PHY_PAGE_SELECT_REG     0x1DU /*!< The PHY page select register. */
+
+/*! @brief Defines the PHY AR8031DS ID number. */
+#define PHY_CONTROL_ID1 0x004DU /*!< The PHY ID1 . */
+
+/*! @brief Defines the mask flag in specific status register. */
+#define PHY_SSTATUS_LINKSTATUS_MASK 0x0400U /*!< The PHY link status mask. */
+#define PHY_SSTATUS_LINKSPEED_MASK  0xC000U /*!< The PHY link speed mask. */
+#define PHY_SSTATUS_LINKDUPLEX_MASK 0x2000U /*!< The PHY link duplex mask. */
+#define PHY_SSTATUS_LINKSPEED_SHIFT 14     /*!< The link speed shift */
+
+/*! @brief Defines the PHY AR8031DS extra page and the registers in specified page. */
+#define PHY_PAGE_RGMII_TXRX_DELAY_ADDR 0x05U   /*!< The register page including RGMII TX/RX delay setting. */
+#define PHY_RGMII_TX_DELAY_REG         0x1EU   /*!< The RGMII TXC delay register. */
+#define PHY_RGMII_RX_DELAY_REG         0x1EU   /*!< The RGMII RXC delay register. */
+#define PHY_RGMII_TX_DELAY_MASK        0x100U  /*!< The RGMII TXC delay mask. */
+#define PHY_RGMII_RX_DELAY_MASK        0x8000U /*!< The RGMII RXC delay mask. */
+
+/*! @brief MDIO MMD Devices .*/
+#define PHY_MDIO_MMD_PCS 3U
+#define PHY_MDIO_MMD_AN  7U
+
+/*! @brief MDIO MMD Physical Coding layer device registers .*/
+#define PHY_MDIO_PCS_EEE_CAP 0x14U /* EEE capability */
+
+/*! @brief MDIO MMD AutoNegotiation device registers .*/
+#define PHY_MDIO_AN_EEE_ADV 0x3CU /* EEE advertisement */
+
+/*! @brief MDIO MMD EEE mask flags. (common for adv and cap) */
+#define PHY_MDIO_EEE_100TX 0x2U
+#define PHY_MDIO_EEE_1000T 0x4U
+
+/*! @brief Defines the timeout macro. */
+#define PHY_READID_TIMEOUT_COUNT 1000U
+
+/*! @brief Defines the PHY MMD data access mode. */
+typedef enum _phy_mmd_access_mode
+{
+    kPHY_MMDAccessNoPostIncrement = (1U << 14), /*!< ENET PHY MMD access data with no address post increment. */
+    kPHY_MMDAccessRdWrPostIncrement =
+        (2U << 14),                             /*!< ENET PHY MMD access data with Read/Write address post increment. */
+    kPHY_MMDAccessWrPostIncrement = (3U << 14), /*!< ENET PHY MMD access data with Write address post increment. */
+} phy_mmd_access_mode_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+static status_t PHY_AR8031DS_MMD_SetDevice(phy_handle_t *handle,
+                                           uint8_t device,
+                                           uint16_t addr,
+                                           phy_mmd_access_mode_t mode);
+static inline status_t PHY_AR8031DS_MMD_ReadData(phy_handle_t *handle, uint32_t *data);
+static inline status_t PHY_AR8031DS_MMD_WriteData(phy_handle_t *handle, uint32_t data);
+static status_t PHY_AR8031DS_MMD_Read(phy_handle_t *handle, uint8_t device, uint16_t addr, uint32_t *data);
+static status_t PHY_AR8031DS_MMD_Write(phy_handle_t *handle, uint8_t device, uint16_t addr, uint32_t data);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+const phy_operations_t phyar8031ds_ops = {.phyInit            = PHY_AR8031DS_Init,
+                                          .phyWrite           = PHY_AR8031DS_Write,
+                                          .phyRead            = PHY_AR8031DS_Read,
+                                          .getAutoNegoStatus  = PHY_AR8031DS_GetAutoNegotiationStatus,
+                                          .getLinkStatus      = PHY_AR8031DS_GetLinkStatus,
+                                          .getLinkSpeedDuplex = PHY_AR8031DS_GetLinkSpeedDuplex,
+                                          /*.setLinkSpeedDuplex = PHY_AR8031DS_SetLinkSpeedDuplex,*/
+                                          .enableLoopback     = PHY_AR8031DS_EnableLoopback};
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+status_t PHY_AR8031DS_Init(phy_handle_t *handle, const phy_config_t *config)
+{
+    uint32_t counter = PHY_READID_TIMEOUT_COUNT;
+    status_t result;
+    uint32_t regValue = 0U;
+
+    /* Init MDIO interface. */
+    MDIO_Init(handle->mdioHandle);
+
+    /* Assign phy address. */
+    handle->phyAddr = config->phyAddr;
+
+    /* Check PHY ID. */
+    do
+    {
+        result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_ID1_REG, &regValue);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+        counter--;
+    } while ((regValue != PHY_CONTROL_ID1) && (counter != 0U));
+
+    if (counter == 0U)
+    {
+        return kStatus_Fail;
+    }
+
+    /* Reset PHY. */
+    result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
+    if (result != kStatus_Success)
+    {
+        return result;
+    }
+
+    /* The RGMII specifies output TXC/RXC and TXD/RXD without any clock skew. Need to add skew on clock line
+       to make sure the other side sample right data. This can also be done in PCB traces. */
+    result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_PAGE_SELECT_REG, PHY_PAGE_RGMII_TXRX_DELAY_ADDR);
+    if (result != kStatus_Success)
+    {
+        return result;
+    }
+    /* Set Tx Delay. */
+    result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_RGMII_TX_DELAY_REG, &regValue);
+    if (result == kStatus_Success)
+    {
+        regValue |= PHY_RGMII_TX_DELAY_MASK;
+        result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_RGMII_TX_DELAY_REG, regValue);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+    }
+    else
+    {
+        return result;
+    }
+    /* Set Rx Delay. */
+    result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_RGMII_RX_DELAY_REG, &regValue);
+    if (result == kStatus_Success)
+    {
+        regValue |= PHY_RGMII_RX_DELAY_MASK;
+        result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_RGMII_RX_DELAY_REG, regValue);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+    }
+    else
+    {
+        return result;
+    }
+    /* Restore to default page 0 */
+    result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_PAGE_SELECT_REG, 0x0);
+    if (result != kStatus_Success)
+    {
+        return result;
+    }
+
+#if 0
+    /* Energy Efficient Ethernet configuration */
+    if (config->enableEEE)
+    {
+        /* Get capabilities */
+        result = PHY_AR8031DS_MMD_Read(handle, PHY_MDIO_MMD_PCS, PHY_MDIO_PCS_EEE_CAP, &regValue);
+        if (result == kStatus_Success)
+        {
+            /* Enable EEE for 100TX and 1000T */
+            result = PHY_AR8031DS_MMD_Write(handle, PHY_MDIO_MMD_AN, PHY_MDIO_AN_EEE_ADV,
+                                            regValue & (PHY_MDIO_EEE_1000T | PHY_MDIO_EEE_100TX));
+        }
+    }
+    else
+#endif
+    {
+        result = PHY_AR8031DS_MMD_Write(handle, PHY_MDIO_MMD_AN, PHY_MDIO_AN_EEE_ADV, 0);
+    }
+    if (result != kStatus_Success)
+    {
+        return result;
+    }
+
+    if (config->autoNeg)
+    {
+        /* Set the auto-negotiation. */
+        result =
+            MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_AUTONEG_ADVERTISE_REG,
+                       PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK | PHY_10BASETX_FULLDUPLEX_MASK |
+                           PHY_10BASETX_HALFDUPLEX_MASK | PHY_IEEE802_3_SELECTOR_MASK);
+        if (result == kStatus_Success)
+        {
+            result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_1000BASET_CONTROL_REG,
+                                PHY_1000BASET_FULLDUPLEX_MASK);
+            if (result == kStatus_Success)
+            {
+                result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, &regValue);
+                if (result == kStatus_Success)
+                {
+                    result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG,
+                                        (regValue | PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
+                }
+            }
+        }
+    }
+    else
+    {
+        /* Disable isolate mode */
+        result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, &regValue);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+        regValue &= ~PHY_BCTL_ISOLATE_MASK;
+        result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+
+        /* Disable the auto-negotiation and set user-defined speed/duplex configuration. */
+        result = PHY_AR8031DS_SetLinkSpeedDuplex(handle, config->speed, config->duplex);
+    }
+    return result;
+}
+
+status_t PHY_AR8031DS_Write(phy_handle_t *handle, uint32_t phyReg, uint32_t data)
+{
+    return MDIO_Write(handle->mdioHandle, handle->phyAddr, phyReg, data);
+}
+
+status_t PHY_AR8031DS_Read(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr)
+{
+    return MDIO_Read(handle->mdioHandle, handle->phyAddr, phyReg, dataPtr);
+}
+
+status_t PHY_AR8031DS_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status)
+{
+    assert(status);
+
+    status_t result;
+    uint32_t regValue;
+
+    *status = false;
+
+    /* Check auto negotiation complete. */
+    result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICSTATUS_REG, &regValue);
+    if (result == kStatus_Success)
+    {
+        if ((regValue & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0U)
+        {
+            *status = true;
+        }
+    }
+    return result;
+}
+
+status_t PHY_AR8031DS_GetLinkStatus(phy_handle_t *handle, bool *status)
+{
+    assert(status);
+
+    status_t result;
+    uint32_t regValue;
+
+    /* Read the basic status register. */
+    result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_SPECIFIC_STATUS_REG, &regValue);
+    if (result == kStatus_Success)
+    {
+        if ((PHY_SSTATUS_LINKSTATUS_MASK & regValue) != 0U)
+        {
+            /* Link up. */
+            *status = true;
+        }
+        else
+        {
+            /* Link down. */
+            *status = false;
+        }
+    }
+    return result;
+}
+
+status_t PHY_AR8031DS_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex)
+{
+    assert(!((speed == NULL) && (duplex == NULL)));
+
+    status_t result;
+    uint32_t regValue;
+
+    /* Read the status register. */
+    result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_SPECIFIC_STATUS_REG, &regValue);
+    if (result == kStatus_Success)
+    {
+        if (speed != NULL)
+        {
+            switch ((regValue & PHY_SSTATUS_LINKSPEED_MASK) >> PHY_SSTATUS_LINKSPEED_SHIFT)
+            {
+                case (uint32_t)kPHY_Speed10M:
+                    *speed = kPHY_Speed10M;
+                    break;
+                case (uint32_t)kPHY_Speed100M:
+                    *speed = kPHY_Speed100M;
+                    break;
+                case (uint32_t)kPHY_Speed1000M:
+                    *speed = kPHY_Speed1000M;
+                    break;
+                default:
+                    *speed = kPHY_Speed10M;
+                    break;
+            }
+        }
+
+        if (duplex != NULL)
+        {
+            if ((regValue & PHY_SSTATUS_LINKDUPLEX_MASK) != 0U)
+            {
+                *duplex = kPHY_FullDuplex;
+            }
+            else
+            {
+                *duplex = kPHY_HalfDuplex;
+            }
+        }
+    }
+    return result;
+}
+
+status_t PHY_AR8031DS_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex)
+{
+    status_t result;
+    uint32_t regValue;
+
+    result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, &regValue);
+    if (result == kStatus_Success)
+    {
+        /* Disable the auto-negotiation and set according to user-defined configuration. */
+        regValue &= ~PHY_BCTL_AUTONEG_MASK;
+        if (speed == kPHY_Speed1000M)
+        {
+            regValue &= ~PHY_BCTL_SPEED0_MASK;
+            regValue |= PHY_BCTL_SPEED1_MASK;
+        }
+        else if (speed == kPHY_Speed100M)
+        {
+            regValue |= PHY_BCTL_SPEED0_MASK;
+            regValue &= ~PHY_BCTL_SPEED1_MASK;
+        }
+        else
+        {
+            regValue &= ~PHY_BCTL_SPEED0_MASK;
+            regValue &= ~PHY_BCTL_SPEED1_MASK;
+        }
+        if (duplex == kPHY_FullDuplex)
+        {
+            regValue |= PHY_BCTL_DUPLEX_MASK;
+        }
+        else
+        {
+            regValue &= ~PHY_BCTL_DUPLEX_MASK;
+        }
+        result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
+    }
+    return result;
+}
+
+status_t PHY_AR8031DS_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable)
+{
+    /* This PHY only supports local loopback. */
+    assert(mode == kPHY_LocalLoop);
+
+    status_t result;
+    uint32_t regValue;
+
+    /* Set the loop mode. */
+    if (enable)
+    {
+        if (speed == kPHY_Speed1000M)
+        {
+            regValue = PHY_BCTL_SPEED1_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
+        }
+        else if (speed == kPHY_Speed100M)
+        {
+            regValue = PHY_BCTL_SPEED0_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
+        }
+        else
+        {
+            regValue = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
+        }
+        result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, regValue);
+    }
+    else
+    {
+        /* First read the current status in control register. */
+        result = MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG, &regValue);
+        if (result == kStatus_Success)
+        {
+            regValue &= ~PHY_BCTL_LOOP_MASK;
+            result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_BASICCONTROL_REG,
+                                (regValue | PHY_BCTL_RESTART_AUTONEG_MASK));
+        }
+    }
+    return result;
+}
+
+static status_t PHY_AR8031DS_MMD_SetDevice(phy_handle_t *handle,
+                                           uint8_t device,
+                                           uint16_t addr,
+                                           phy_mmd_access_mode_t mode)
+{
+    status_t result = kStatus_Success;
+
+    /* Set Function mode of address access(b00) and device address. */
+    result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_CONTROL_REG, device);
+    if (result != kStatus_Success)
+    {
+        return result;
+    }
+
+    /* Set register address. */
+    result = MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_DATA_REG, addr);
+    if (result != kStatus_Success)
+    {
+        return result;
+    }
+
+    /* Set Function mode of data access(b01~11) and device address. */
+    result =
+        MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_CONTROL_REG, (uint32_t)mode | (uint32_t)device);
+    return result;
+}
+
+static inline status_t PHY_AR8031DS_MMD_ReadData(phy_handle_t *handle, uint32_t *data)
+{
+    return MDIO_Read(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_DATA_REG, data);
+}
+
+static inline status_t PHY_AR8031DS_MMD_WriteData(phy_handle_t *handle, uint32_t data)
+{
+    return MDIO_Write(handle->mdioHandle, handle->phyAddr, PHY_MMD_ACCESS_DATA_REG, data);
+}
+
+static status_t PHY_AR8031DS_MMD_Read(phy_handle_t *handle, uint8_t device, uint16_t addr, uint32_t *data)
+{
+    status_t result = kStatus_Success;
+    result          = PHY_AR8031DS_MMD_SetDevice(handle, device, addr, kPHY_MMDAccessNoPostIncrement);
+    if (result == kStatus_Success)
+    {
+        result = PHY_AR8031DS_MMD_ReadData(handle, data);
+    }
+    return result;
+}
+
+static status_t PHY_AR8031DS_MMD_Write(phy_handle_t *handle, uint8_t device, uint16_t addr, uint32_t data)
+{
+    status_t result = kStatus_Success;
+
+    result = PHY_AR8031DS_MMD_SetDevice(handle, device, addr, kPHY_MMDAccessNoPostIncrement);
+    if (result == kStatus_Success)
+    {
+        result = PHY_AR8031DS_MMD_WriteData(handle, data);
+    }
+    return result;
+}
diff --git a/component/phy/device/phyar8031ds/fsl_phyar8031ds.h b/component/phy/device/phyar8031ds/fsl_phyar8031ds.h
new file mode 100644
index 0000000..2da7ce3
--- /dev/null
+++ b/component/phy/device/phyar8031ds/fsl_phyar8031ds.h
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2020 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_PHYAR8031DS_H_
+#define _FSL_PHYAR8031DS_H_
+
+#include "fsl_phy.h"
+
+/*!
+ * @addtogroup phy_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief PHY driver version */
+#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+
+/*! @brief PHY operations structure. */
+extern const phy_operations_t phyar8031ds_ops;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name PHY Driver
+ * @{
+ */
+
+/*!
+ * @brief Initializes PHY.
+ *
+ *  This function initialize PHY.
+ *
+ * @param handle       PHY device handle.
+ * @param config       Pointer to structure of phy_config_t.
+ * @retval kStatus_Success  PHY initialization succeeds
+ * @retval kStatus_Fail  PHY initialization fails
+ * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
+ */
+status_t PHY_AR8031DS_Init(phy_handle_t *handle, const phy_config_t *config);
+
+/*!
+ * @brief PHY Write function. This function writes data over the SMI to
+ * the specified PHY register. This function is called by all PHY interfaces.
+ *
+ * @param handle  PHY device handle.
+ * @param phyReg  The PHY register.
+ * @param data    The data written to the PHY register.
+ * @retval kStatus_Success     PHY write success
+ * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
+ */
+status_t PHY_AR8031DS_Write(phy_handle_t *handle, uint32_t phyReg, uint32_t data);
+
+/*!
+ * @brief PHY Read function. This interface reads data over the SMI from the
+ * specified PHY register. This function is called by all PHY interfaces.
+ *
+ * @param handle   PHY device handle.
+ * @param phyReg   The PHY register.
+ * @param dataPtr  The address to store the data read from the PHY register.
+ * @retval kStatus_Success  PHY read success
+ * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
+ */
+status_t PHY_AR8031DS_Read(phy_handle_t *handle, uint32_t phyReg, uint32_t *dataPtr);
+
+/*!
+ * @brief Gets the PHY auto-negotiation status.
+ *
+ * @param handle   PHY device handle.
+ * @param status   The auto-negotiation status of the PHY.
+ *         - true the auto-negotiation is over.
+ *         - false the auto-negotiation is on-going or not started.
+ * @retval kStatus_Success   PHY gets status success
+ * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
+ */
+status_t PHY_AR8031DS_GetAutoNegotiationStatus(phy_handle_t *handle, bool *status);
+
+/*!
+ * @brief Gets the PHY link status.
+ *
+ * @param handle   PHY device handle.
+ * @param status   The link up or down status of the PHY.
+ *         - true the link is up.
+ *         - false the link is down.
+ * @retval kStatus_Success   PHY gets link status success
+ * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
+ */
+status_t PHY_AR8031DS_GetLinkStatus(phy_handle_t *handle, bool *status);
+
+/*!
+ * @brief Gets the PHY link speed and duplex.
+ *
+ * @brief This function gets the speed and duplex mode of PHY. User can give one of speed
+ * and duplex address paramter and set the other as NULL if only wants to get one of them.
+ *
+ * @param handle   PHY device handle.
+ * @param speed    The address of PHY link speed.
+ * @param duplex   The link duplex of PHY.
+ * @retval kStatus_Success   PHY gets link speed and duplex success
+ * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
+ */
+status_t PHY_AR8031DS_GetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t *speed, phy_duplex_t *duplex);
+
+/*!
+ * @brief Sets the PHY link speed and duplex.
+ *
+ * @param handle   PHY device handle.
+ * @param speed    Specified PHY link speed.
+ * @param duplex   Specified PHY link duplex.
+ * @retval kStatus_Success   PHY gets status success
+ * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
+ */
+status_t PHY_AR8031DS_SetLinkSpeedDuplex(phy_handle_t *handle, phy_speed_t speed, phy_duplex_t duplex);
+
+/*!
+ * @brief Enables/disables PHY loopback.
+ *
+ * @param handle   PHY device handle.
+ * @param mode     The loopback mode to be enabled, please see "phy_loop_t".
+ * All loopback modes should not be set together, when one loopback mode is set
+ * another should be disabled.
+ * @param speed    PHY speed for loopback mode.
+ * @param enable   True to enable, false to disable.
+ * @retval kStatus_Success  PHY loopback success
+ * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
+ */
+status_t PHY_AR8031DS_EnableLoopback(phy_handle_t *handle, phy_loop_t mode, phy_speed_t speed, bool enable);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_PHY_H_ */
diff --git a/component/phy/fsl_phy.h b/component/phy/fsl_phy.h
index ccfc664..1288fb0 100644
--- a/component/phy/fsl_phy.h
+++ b/component/phy/fsl_phy.h
@@ -29,7 +29,8 @@
 #define PHY_BCTL_LOOP_MASK            0x4000U /*!< The PHY loop bit mask. */
 #define PHY_BCTL_RESET_MASK           0x8000U /*!< The PHY reset bit mask. */
 #define PHY_BCTL_SPEED_100M_MASK      0x2000U /*!< The PHY 100M speed mask. */
-#define PHY_BCTL_SPEED1_MASK          0x40U   /*!< The PHY speed 1 mask.*/
+#define PHY_BCTL_SPEED1_MASK          0x0040U /*!< The PHY speed 1 mask.*/
+#define PHY_BCTL_ISOLATE_MASK         0x0400U /*!< The PHY isolate mask.*/
 
 /*! @brief Defines the mask flag in basic status register. */
 #define PHY_BSTATUS_LINKSTATUS_MASK  0x0004U /*!< The PHY link status mask. */
@@ -43,6 +44,7 @@
 #define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
 #define PHY_10BASETX_FULLDUPLEX_MASK  0x040U /*!< The PHY has the 10M full duplex ability.*/
 #define PHY_10BASETX_HALFDUPLEX_MASK  0x020U /*!< The PHY has the 10M full duplex ability.*/
+#define PHY_IEEE802_3_SELECTOR_MASK   0x001U /*!< The message type being sent by Auto-Nego.*/
 
 /*! @brief Defines the mask flag in the 1000BASE-T control register. */
 #define PHY_1000BASET_FULLDUPLEX_MASK 0x200U /*!< The PHY has the 1000M full duplex ability.*/
diff --git a/firmware/aws_ota/main_enet.c b/firmware/aws_ota/main_enet.c
index 3c02294..ca7531e 100644
--- a/firmware/aws_ota/main_enet.c
+++ b/firmware/aws_ota/main_enet.c
@@ -60,7 +60,8 @@
 #include "lwip/netifapi.h"
 
 #ifdef SOC_IMXRT1170_SERIES
-#include "fsl_phyrtl8211f.h"
+//#include "fsl_phyrtl8211f.h"
+#include "fsl_phyar8031ds.h"
 #else
 #include "fsl_phyksz8081.h"
 #endif
@@ -79,7 +80,8 @@
 #define EXAMPLE_PHY_ADDRESS BOARD_ENET1_PHY_ADDRESS
 
 /* PHY operations. */
-#define EXAMPLE_PHY_OPS phyrtl8211f_ops
+//#define EXAMPLE_PHY_OPS phyrtl8211f_ops
+#define EXAMPLE_PHY_OPS phyar8031ds_ops
 
 /* ENET clock frequency. */
 #define EXAMPLE_CLOCK_FREQ CLOCK_GetRootClockFreq(kCLOCK_Root_Bus)
diff --git a/target/evkmimxrt1170/board/board.h b/target/evkmimxrt1170/board/board.h
index c316dcd..088979b 100644
--- a/target/evkmimxrt1170/board/board.h
+++ b/target/evkmimxrt1170/board/board.h
@@ -105,7 +105,8 @@
 #define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
 
 /*! @brief The ENET1 PHY address. */
-#define BOARD_ENET1_PHY_ADDRESS (0x01U) /* Phy address of enet port 1. */
+//#define BOARD_ENET1_PHY_ADDRESS (0x01U) /* Phy address of enet port 1. */
+#define BOARD_ENET1_PHY_ADDRESS (0x00U) /* Phy address of enet port 1. */
 
 /* @brief The EMVSIM SMARTCARD PHY configuration. */
 #define BOARD_SMARTCARD_MODULE                (EMVSIM1)      /*!< SMARTCARD communicational module instance */
